A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS

机译：具有90nm CMOS中的32KB 10T亚阈值SRAM阵列，位交错和差分读取方案

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The paper presents an SRAM array with bit interleaving and read scheme. The SRAM test-chip is fabricated in a 90nm CMOS technology. For leakage comparison, 49 kb arrays are implemented for both the conventional 6T cell and 10T cell. The leakage power cons

机译：本文介绍了具有位交织和读取方案的SRAM阵列。 SRAM测试芯片以90nm CMOS技术制造。对于泄漏比较，为传统的6T电池和10T细胞实现49kb阵列。泄漏功率缺点

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《IEEE International Solid-State Circuits Conference》|2008年||共235页
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Ik Joon Chang; Jae-Joon Kim; Park S.P.; Roy K.;
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中图分类 TN43-53;
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CMOS memory circuits; SRAM chips; CMOS; SRAM array; bit interleaving; differential read; frequency 31.25 kHz; frequency 500 Hz; memory size 32 KByte; power 0.123 muW; size 90 nm; voltage 0.16 V; voltage 0.18 V;

机译：CMOS 存储器电路;SRAM芯片;CMOS;SRAM 阵列;比特交织;差动读操作;频率 31.25 千赫;频率 500 赫兹;存储器大小为32 千字节;功率 0.123 MUW;尺寸 90 纳米;电压 0.16 伏;电压 0.18 V;

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专利

1. A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS [J] . Chang I. J., Kim J.-J., Park S. P., IEEE Journal of Solid-State Circuits . 2009,第2期

机译：在90 nm CMOS中具有位交错和差分读取方案的32 kb 10T次阈值SRAM阵列
2. Design and Iso-Area $V_{min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS [J] . Chang M.-H., Chiu Y.-T., Hwang W. Circuits and Systems II: Express Briefs, IEEE Transactions on . 2012,第7期

机译：在65 nm CMOS中采用位交错方案的9T亚阈值SRAM的设计和等值面积$ V_ {min} $分析
3. Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS [J] . Gupta Shourya, Gupta Kirti, Calhoun Benton H., IEEE transactions on circuits and systems . I , Regular papers . 2019,第3期

机译：低功耗近阈值10T SRAM位单元，具有增强的与数据无关的读取端口泄漏功能，用于32nm CMOS阵列增强
4. A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS [C] . Ik Joon Chang, Jae-Joon Kim, Park S.P., IEEE International Solid-State Circuits Conference . 2008

机译：具有90nm CMOS中的32KB 10T亚阈值SRAM阵列，位交错和差分读取方案
5. Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier [O] . Jong-Ryul Yang, Seong-Tae Han, Donghyun Baek 2017

机译：带有亚阈值放大器的差分CMOS亚太赫兹检测器
6. A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS [O] . Chang, Ik Joon, Kim, Jae-Joon, Park, Sang Phill, 2008

机译：具有位交织和差分读取方案的32kb 10T亚阈值SRAM阵列在90nm CMOS中

A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS

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