Manual Assembly of 400um Bumped-Die GaN Power Semiconductor Devices

摘要

Until recently, power semiconductors were usually produced as TO, power-PAK, and D-PAK stylepackaging, due to die size, thermal dissipation requirements, and the vertical flow of current through the devices.The introduction of GaN to power semiconductors has allowed manufactures to produce devices with approximately9% the footprint of similar rated D-PAK Si MOSFETs. In addition, GaN semiconductors have much bettertheoretical limits of specific on-resistance to breakdown voltage, when compared to Si and SiC. As of now, GaNdevices offer very good performance at much less the cost of SiC, very small footprints, no reverse recovery losses ofa body diode, very low R_(DS(ON)), and very fast turn-on and turn-off times due to Q_(GS) in single-digit nC range. GaNsemiconductors are expected to make vast improvements over the next decade. Unfortunately, this decrease inpackage size has made design prototyping significantly more challenging. Traditional manual solder iron assemblyis not sufficient for these devices. Difficulties include board design, device handling, alignment, solder reflow, fluxresidue removal, and post-assembly inspection. The EPC 2014 and 2015 devices both have a 4mm pitch and are1.85mm~2 and 6.70mm~2, respectively. In many situations, the decreased pitch and small overall size of these devicesmandate the use of automated assembly equipment, such as a pick & place, to ensure quality and repeatability ofassembly. However, this may not be feasible for initial prototyping, due to cost and time constraints. Here we willpresent a technique for manual assembly of these chip scale devices, applied specifically to the EPC 2014 and 2015.This should decrease the cost and turn time for prototype assembly when utilizing these types of chip scale packagedpower semiconductor devices.