Low power SAR ADC with two-step switching scheme in 65 nm standard CMOS process

摘要

The low power successive approximation register (SAR) analog to digital converter (ADC), which implements the two-step switching, is designed and simulated in 65 nm CMOS of ST Microelectronics. The two-step switching allows to benefit from the more energy-efficient switching because of the use of three voltage levels without any requirements for stability and accuracy of the third voltage level. Post-layout simulations of the proposed ADC were performed. It consumes 200 nW at 0.5 V supply voltage and 100 kHz sampling rate. The effective number of bits (ENOB) is 9.5 bits, while the differential and integral nonlinearities do not exceed 0.5 LSB. The utilized die area is only 0.027 mm2.