adders; application specific integrated circuits; digital signal processing chips; finite state machines; hardware description languages; logic design; multiplying circuits; pipeline arithmetic; ASIC; DSP; FSM; Verilog HDL; Xilinx Virtex-6 XC6VLX75T-3-FF484 FPGA; adders; finite state machine; hardware resources; high-speed pipelined multiplier; logical resources; multiplication process; partial products addition; pipelined multiplier design; pipelined multiplier hardware design; unsigned multiplication; unsigned pipelined multiplier; Adders; Clocks; Delays; Field programmable gate arrays; Hardware; Hardware design languages; Multiplexing; ASIC; FPGA; FSM; Maximum frequency; Pipeline;
机译:基于Verilog / VHDL的FPGA中可综合的32位四级流水线RISC处理器的设计与实现
机译:基于吠陀数学的高速32位流水线乘法器的FPGA设计,仿真和原型设计
机译:改进的无逆Berlerkamp-Massey算法和规范域乘数的Verilog HDL优化设计和仿真
机译:使用Verilog HDL的基于FSM的32位无符号高速流水线乘法器的高效设计
机译:使用Verilog HDL的管道FFT架构实现。
机译:Q-nexus:专为ChIP-nexus设计的全面而高效的分析管道
机译:高速32位有符号/无符号流水线乘法器