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Effects of Tin and Copper Nanotexturization on Tin Whisker Formation

机译:锡和铜纳米织构化对锡晶须形成的影响

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The physical mechanisms behind tin whisker formation in pure tin (Sn) films continue to elude the microelectronics industry. Despite modest advances in whisker mitigation techniques (i.e., barrier metal underlayers, substrate/film annealing, etc.) and encapsulation, ways to fundamentally prevent whiskers from forming remain unknown. It has been said that tin plating thicknesses of <0.5 um or >20um are "whisker inhibiting"[3,6]. In the case of the former claim, it may be argued that as film grains approach an equiaxed proportion (i.e., the average columnar grain height is roughly equivalent to the average grain diameter), stress compensation is no longer preferential to the normal direction with respect to the plated film. Grain morphology has often been pointed to in the literature as a likely factor in Sn whisker formation due to the fact that SnPb, which does not whisker, has equiaxed grains while pure Sn exhibits columnar grain growth, which is only equiaxed when the film thickness matches the average grain diameter. Our work examines the effect of adding grain refiners during tin electroplating, with particular focus on the 'as-deposited' film morphology and the associated incidence of whiskering. We have included polycrystalline Sn 'control samples' in our study, and as an extension of our previous work[l], we have compared the structure and whiskering incidence of nanotexturized Sn on both polycrystalline and nanocrystalline Cu underlayers.
机译:纯锡(Sn)薄膜中锡晶须形成的物理机制仍在微电子工业中空缺。尽管缓解晶须的技术(即阻挡金属底层,衬底/膜退火等)和封装技术取得了适度的进步,但从根本上防止晶须形成的方法仍然未知。据说<0.5 um或> 20um的镀锡厚度“抑制晶须” [3,6]。在前一项权利要求的情况下,可能会争辩说,当薄膜晶粒接近等轴比例时(即,平均柱状晶粒高度大致等于平均晶粒直径),应力补偿不再相对于法线方向优先。镀膜。文献中经常指出晶粒形态是锡晶须形成的可能因素,这是由于以下事实:不晶须的SnPb具有等轴晶,而纯锡表现出柱状晶粒生长,仅当膜厚匹配时才等轴晶。平均晶粒直径。我们的工作研究了在锡电镀过程中添加晶粒细化剂的效果,尤其关注“沉积状态”的薄膜形态和相关的晶须发生率。我们已经在研究中包括了多晶锡的“对照样品”,并且作为我们以前工作的扩展[1],我们比较了多晶和纳米晶Cu底层上纳米结构化Sn的结构和晶须发生率。

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