The rapid growth of wireless consumer electronics products is driving demand for cost effective and small form factor packaging solutions. While front end silicon technologies have followed Moore's law by device scaling, the back end infrastructure has lagged in similar advancements. This has created an interconnect gap whereby the signal speed achieved on silicon is significantly higher than the speed achieved on the printed circuit boards. Innovative advancements such as Fan-out wafer level packaging technology were introduced to address the pad limitation consideration with traditional wafer level packaging while delivering miniaturization and potential low cost packaging advantages. It does this by extending the package interconnect area beyond the front end chip size to allow increased number of I/O required for large die sizes. This technology allows tested-good dice to be reconstituted into wafer form, and interconnections are formed using wafer level processing technology. Die positioning control within the reconstituted wafer significantly affects downstream process requirements. The use of high productivity pick and place equipment with multiple gantries create challenges for the lithographic tool alignment when die placements from each gantry are not identical. This will be especially true in the future as the placement tolerances are reduced for advanced products containing multiple die types. This paper describes the inaccuracy in pick and place from single and dual gantry operation, and investigates lithographic alignment methods specifically developed to minimize pick and place errors from multiple gantry operation. The current single zone alignment algorithm was extended to create multiple selection zones to match the multiple gantries of the die pick and place equipment. The enhanced capability allows the flexibility to conduct a separate alignment mapping for different zones of the reconstituted Fan-out wafers. The dual zone mapping gave more effe--ctive compensation for a gantry matching error, resulting in better than 50% improvement in registration error compared with a single zone mapping. This provides significantly superior alignment control for next generation devices fabricated with fan out wafer level packaging process.
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