Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

摘要

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by thePVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed onthe determination and optimization of the important parameters for each of the key enabling technologies. Also,leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of thefabricated TSVs are provided and examined.