ASSESSMENT AND CHARACTERIZATION OF STRESS INDUCED BY VIA-FIRST TSV TECHNOLOGY

摘要

Through Silicon Via (TSV) is a key enabling technology for 3D stacking. One of the main concerns regardingthe TSV introduction inside the IC fabrication is the resulting stress build up in the silicon substrate that may inducewarpage or expansion at the wafer level, strain and crystalline defects in the neighboring silicon of the TSV andfinally can impact performances and reliability of the CMOS devices as well. Polysilicon, tungsten and copper arethe three main conductors that are nowadays considered for the TSV fabrication. In a first part of this paper thedifferent factors that contribute to the stress in these tree TSV types including the geometry, the materials and theprocess will be reviewed.After bonding on a temporary carrier and thinning of the substrate to expose the via the stress built up during thefabrication of the TSV can be also revealed by the expansion of the silicon membrane.Thermo-mechanical FEM simulations will be equally introduced and confronted to the experimental findings.We also present some characterizations of silicon defects by chemical revelation around the TSV structures.For characterization of the stress in TSV structures scale different techniques as EBSD, μRaman, XRD will bethen presented.Finally we conclude that with the optimization of some key processing steps, the stress induced in via-firsttechnology may be acceptable for IC integration.