BIST Circuit Design for SRAM Based on the March C- Algorithm

摘要

As the process technology Continues to scale, embedded Static Random Access Memories (SRAMs) testing has become an important subject. Among the current testing technologies, Built-in Self-Test (BIST) is a both time-saving and cost-saving means. By taking into account the embedded SRAM fault model, the March C-algorithm is chosen. It has a higher coverage for common faults of SRAM. This paper is focus on the overall design of a SRAM BIST circuit based on Finite State Machine (FSM).