3-D integration is going to play an important role in the future. Increasing complexity and increasing impact of interconnects to Integrated Circuit (1C) performance makes 3-D more and more attractive. EDA tools for 3-D design hardly exist. We propose a new 3-D standard-cell placer based on quadratic programming. It ensures a reduction of the total wirelength and can deal with standard cells and vertical interconnects simultaneously. The final result is a legalized, design rule compliant and discrete 3-D placement.
展开▼
