首页> 外文会议>22nd International Computer Architecture and High Performance Computing >A Clock Synchronization Strategy for Minimizing Clock Variance at Runtime in High-End Computing Environments
【24h】

A Clock Synchronization Strategy for Minimizing Clock Variance at Runtime in High-End Computing Environments

机译:一种在高端计算环境中最小化运行时时钟差异的时钟同步策略

获取原文

摘要

We present a new software-based clock synchronization scheme that provides high precision time agreement among distributed memory nodes. The technique is designed to minimize variance from a reference chimer during runtime and with minimal time-request latency. Our scheme permits initial unbounded variations in time and corrects both slow and fast chimers (clock skew). An implementation developed within the context of the MPI message passing interface is described and time coordination measurements are presented. Among our results, the mean time variance among a set of nodes improved from 20.0 milliseconds under standard Network Time Protocol (NTP) to 2.29 μsecs under our scheme.
机译:我们提出了一种新的基于软件的时钟同步方案,该方案可在分布式存储节点之间提供高精度的时间协议。该技术旨在在运行时以最小的时间请求延迟最小化与参考嵌合体的差异。我们的方案允许初始的时间无限变化,并校正慢速和快速嵌合(时钟偏斜)。描述了在MPI消息传递接口的上下文中开发的实现,并提出了时间协调度量。在我们的结果中,一组节点之间的平均时间方差从标准网络时间协议(NTP)下的20.0毫秒提高到我们的方案下的2.29微秒。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号