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circuit for minimizing the disturbance of frequency of clock synchronization in phase with a local reference clock circuit
circuit for minimizing the disturbance of frequency of clock synchronization in phase with a local reference clock circuit
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机译:使与本地参考时钟电路同相的时钟同步频率的干扰最小的电路
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摘要
A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.
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