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24.9 Intermittent Resonant Clocking Enabling Power Reduction at any Clock Frequency for 0.37V 980kHz Near-Threshold Logic Circuits

机译：24.9间歇谐振时钟可在任何时钟频率下实现功率降低，适用于0.37V 980kHz近阈值逻辑电路

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Hiroshi Fuketa; Masahiro Nomura; Makoto Takamiya; Takayasu Sakurai;
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年度 2015
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1. Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits [J] . Fuketa H., Nomura M., Takamiya M., IEEE Journal of Solid-State Circuits . 2014,第2期

机译：间歇谐振时钟可在任何时钟频率下降低近/亚阈值逻辑电路的功耗
2. Near-Threshold Computing of Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Circuits [J] . Yangbo Wu, Jianping Hu Journal of Low Power Electronics . 2011,第3期

机译：带有互补传递晶体管逻辑电路的时钟绝热逻辑的近阈值计算
3. Gate Leakage Reduction by Clocked Power Supply of Adiabatic Logic Circuits [J] . Ph.Teichmann, J.Fischer, E.Amirante, Advances in Radio Science . 2005,第14期

机译：通过绝热逻辑电路的时钟电源减少栅极泄漏
4. Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits [C] . Fuketa Hiroshi, Nomura Masahiro, Takamiya Makoto, IEEE International Solid-State Circuits Conference . 2013

机译：间歇谐振时钟可在任何时钟频率下降低0.37V 980kHz近阈值逻辑电路的功率
5. Power reduction in digital systems through local resonant clocking and dynamic threshold MOS. [D] . Drake, Alan James. 2005

机译：通过本地谐振时钟和动态阈值MOS降低数字系统的功耗。
6. Synthesizing genetic sequential logic circuit with clock pulse generator [O] . Chia-Hua Chuang, Chun-Liang Lin 2014

机译：利用时钟脉冲发生器合成遗传时序逻辑电路
7. Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits [O] . Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, 2015

机译：间歇谐振时钟可在任何时钟频率下为近/低阈值逻辑电路实现功率降低
8. Mixed Frequency-Time Approach for Finding the Steady-State Solution of Clocked Analog Circuits [R] . Kundert, K., White, J., Sangiovanni-Vincentelli, A. 1988

机译：寻找时钟模拟电路稳态解的混合频率 - 时间方法

24.9 Intermittent Resonant Clocking Enabling Power Reduction at any Clock Frequency for 0.37V 980kHz Near-Threshold Logic Circuits

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