Process variation tolerant all-digital multiphase DLL for DDR3 interface

摘要

An all-digital multiphase DLL is presented that is robust to delay mismatch due to process variation. Each of four 90° phase shift blocks accurately align each phase to 90° delay using its own ring oscillator and locking delay code. Harmonic locking is protected by a ring oscillator and a counter. An area efficient binary to thermometer converter is proposed to diminish the area overhead due to four delay line controllers. An edge combiner is used for duty cycle correction and clock 2x multiplications. The measured large locking delay code difference between four 90° phase shift delay lines in the proposed DLL implemented in 45nm CMOS process, which corresponds to ±31ps at 800MHz, proves that the DLL corrects significant phase error caused by delay mismatch. Phase shift accuracy errors at 90° and 270° phases are 0.43° and 1.01°, respectively, and output frequency is 1.6GHz with 50% duty cycle at 800MHz. Power consumption is 3.3mW at 800MHz.