A multi-bit cascaded sigma-delta modulator with an oversampled single-bit DAC

摘要

This paper describes a multi-bit cascaded sigma-delta modulator in which an over-sampled single-bit DAC emulates the behavior of a multi-bit DAC. Such an implementation, benefits from the inherent linearity of a single-bit DAC, and avoids the extra loop-delay imposed by dynamic element matching techniques required to linearize multi-bit DACs. The behavior of an oversampled single-bit DAC has been simulated in the context of a complex, continuous-time, cascaded sigma-delta modulator with a 2-bit quantizer, implemented in a standard 90nm CMOS technology. For an input bandwidth of 20MHz and a sampling rate of 500MHz, a peak SNDR of 85dB was achieved with a 4× oversampled DAC.