A 3D Analytical Model for Calculating the On-resistance of Integrated VDMOSFET

摘要

Power Integrated Circuits (PlCs) combine high voltage and/or high current devices monolithically with low voltage control circuits. Since all the contacts of the integrated VDMOSFET are on the top of chip, the calculation of its on-resistance doesnit scale in the same manner as for conventional VDMOSFET. The on-resistance of an integrated VDMOSFET is affected deeply by the placement and number of source ceils. In this paper, a 3D analytical model for calculating the on-resistance of integrated VDMOSFET accurately is developed, and can predict the optimum of placement and number of cells for a minimal specific on-resistance within limited chip area.