This paper investigates the basic mechanisms of hysteretic delay and noise margin variations for floating-body Partially-Depleted SOI CMOS domino circuits in detail. Three cases, based on whether the input signals are "domino input signals" from other domino circuits; "static input signals" from static circuits or latches; or a combination of "domino and static input signals" are examined and differentiated. It is shown that hysteretic delay variation is larger and noise margin worse for the later case with "mixed domino and static input signals." Although the delay and noise margin disparities between the three types of input signals are significant at beginning of the clock cycles, they converge as the circuit approaches steady-state.
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