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The performance impact of block sizes and fetch strategies

机译:块大小和获取策略对性能的影响

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摘要

This paper explores the interactions between a cache's block size, fetch size and fetch policy from the perspective of maximizing system-level performance. It has been previously noted that given a simple fetch strategy the performance optimal block size is almost always four or eight words [10]. If there is even a small cycle time penalty associated with either longer blocks or fetches, then the performance-optimal size is noticeably reduced. In split cache organizations, where the fetch and block sizes of instruction and data caches are all independent design variables, instruction cache block size and fetch size should be the same. For the workload and write-back write policy used in this trace-driven simulation study, the instruction cache block size should be about a factor of two greater than the data cache fetch size, which in turn should equal to or double the data cache block size. The simplest fetch strategy of fetching only on a miss and stalling the CPU until the fetch is complete works well. Complicated fetch strategies do not produce the performance improvements indicated by the accompanying reductions in miss ratios because of limited memory resources and a strong temporal clustering of cache misses. For the environments simulated here, the most effective fetch strategy improved performance by between 1.7% and 4.5% over the simplest strategy described above.

机译:

本文从最大化系统级性能的角度探讨了缓存的块大小,访存大小和访存策略之间的相互作用。以前已经注意到,给定一个简单的获取策略,性能最佳块大小几乎总是四个或八个字[10]。如果甚至有较小的周期时间损失与较长的块或获取相关联,则性能最佳大小会显着减小。在拆分缓存组织中,指令和数据缓存的获取和块大小都是独立的设计变量,指令缓存的块大小和获取大小应该相同。对于此跟踪驱动的模拟研究中使用的工作负载和回写策略,指令高速缓存块大小应比数据高速缓存获取大小大两倍左右,后者又应等于或大于数据高速缓存块的两倍。尺寸。仅在未命中时提取并暂停CPU直到完成提取的最简单的提取策略效果很好。复杂的提取策略由于内存资源有限和高速缓存未命中事件的时间聚集性强,因此无法通过未命中率的降低来提高性能。对于此处模拟的环境,最有效的提取策略比上述最简单的策略将性能提高了1.7%至4.5%。

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