首页> 外文会议>Solid State Device Research Conference, 1991. ESSDERC '91 >9.5ÃÂÃÂ9.5mm²-Area Recrystallization, 6ÃÂÃÂ¿m-Viahole Filling and Thin 1/4ÃÂÃÂ¿m CMOS SOI Designing for Realizing Three-Dimensional Integrated Circuit

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9.5ÃÂÃÂ9.5mm²-Area Recrystallization, 6ÃÂÃÂ¿m-Viahole Filling and Thin 1/4ÃÂÃÂ¿m CMOS SOI Designing for Realizing Three-Dimensional Integrated Circuit

机译：9.5mm-9.5mm ^{2 区域重结晶，6μm的通孔填充和1 /4μm的薄CMOS SOI实现三维集成电路的设计}

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Several key technologies;large-area recryatallization technique, viahole-filling, and scaled thin SOI devices, have been prepared for realizing 3D LSI.

机译：为了实现3D LSI，已经准备了几项关键技术;大面积再结晶技术，通孔填充和按比例缩小的薄型SOI器件。

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《Solid State Device Research Conference, 1991. ESSDERC '91》|1991年|175-178|共4页
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Onga S.; Kambayashi S.; Yoshimi M.; Natori K.; Kashiwagi M.;
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9.5ÃÂÃÂ9.5mm2-Area Recrystallization, 6ÃÂÃÂ¿m-Viahole Filling and Thin 1/4ÃÂÃÂ¿m CMOS SOI Designing for Realizing Three-Dimensional Integrated Circuit

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9.5ÃÂÃÂ9.5mm²-Area Recrystallization, 6ÃÂÃÂ¿m-Viahole Filling and Thin 1/4ÃÂÃÂ¿m CMOS SOI Designing for Realizing Three-Dimensional Integrated Circuit