A 10b 320 MS/s 40 mW open-loop interpolated pipeline ADC

摘要

An open-loop interpolated pipeline ADC is proposed. Weight controlled capacitor arrays are introduced to realize an interpolation and a pipelined operation with open-loop amplifiers. The 10-bit ADC fabricated in 90 nm CMOS demonstrates ENOB of 8.5b over 80 MHz bandwidth (BW) and a conversion rate of 320 MS/s without linearity compensation and consumes 40 mW. The FoMs are 780 fJ/c.-s. defined by the 80 MHz BW and 390 fJ/c.-s. defined by the 320 MSps conversion rate with a BW of 80 MHz.