A 2.8 mW/Gb/s quad-channel 8.5–11.4 Gb/s quasi-digital transceiver in 28 nm CMOS

摘要

A SerDes operating from 8.5 to 11.4 Gb/s using nearly all CMOS digital circuits is presented. The transmitter achieves up to 1 Vdpp output swing with a DDJ as low as 2.7 ps. The receiver achieves an input sensitivity of less than 17 mVdpp. The chip is capable of transmitting and receiving data on an FR4 channel with 21 dB loss at Nyquist at a BER < 10−12. The power consumption per Tx/Rx pair is 28.5 mW, and the active area is 0.047 mm2 in 28 nm CMOS. The chip reports the minimum SerDes area in the published literature.