A 780 mW 4 $times$ 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS

摘要

This paper describes a reconfigurable 4 28 Gb/s transceiver supporting 100 GbE/40 GbE standards. In each lane, the transmitter incorporates a 3-tap FIR with independent output phase adjustment, and the receiver has a half-rate CDR with a dedicated eye-monitor channel. There is a global resonant clock distribution network implemented using programmable distributed on-chip inductors. Implemented in a 40 nm CMOS process, the TX output measures and . The RX jitter tolerance is at 80 MHz with an input sensitivity of . The transceiver achieves BER on a channel with 20 dB loss at Nyquist, dissipating only 780 mW from a 0.9 V supply for all four lanes at 28 Gb/s operation.