This paper proposes a new FPGA based architecture for digital pulse width modulators which takes advantage of dedicated digital clock manager (DCM) blocks present in modern FPGAs and applies manual placement techniques to match internal delays for high linearity. The proposed hybrid DPWM uses a synchronous counter-based coarse-resolution block and a DCM based fine-resolution block implementing a synchronous delay line. The design was successfully implemented on a low-cost Xilinx Spartan-3 FPGA with 9-bit resolution with a switching frequency of 1 MHz. Linearity was manually optimized using the presented technique which reduced the integral non-linearity error by 0.5 LSB.
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