3D wafer or chip stacking by through-silicon vias (TSVs) has brought the industry close to a breakthrough. For fabricating TSV structure, a serious challenge is the front side chemical mechanical planarization (CMP) process and especially non-uniformity within 300 mm post-CMP wafers. This paper makes thorough investigation into front side CMP by studying material removal rate (MRR) selectivity and non-uniformity (NU) in TSV and corresponding copper/TEOS layer removal. MRR and NU of different layers were measured under different polishing down force and hydrogen peroxide concentration, and removal rate selectivity was calculated and compared. The results showed that down force should be controlled to achieve a high material removal rate while greatly maintaining NU in a low level. Hydrogen peroxide concentration had a very strong influence on MRR and selectivity of copper/TEOS oxide and directly leads to via dishing situation, which influence the non-uniformity. Subsequently, an ideal combination of process parameters were achieved to obtain a good result in terms of low non-uniformity. This was applied to TSV polishing to verify performance and stability, conducted in a marathon test including TSV/copper/TEOS wafers. In order to facilitate the explanation of TSV removal, the synergistic effect of different layers and removal mechanism on TSV CMP were explained. This conform to the experiments, which is of great value to further research about profile control in the TSV CMP process.
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