Using Programmable On-Product Clock Generation (OPCG) for Delay Test

摘要

On-product clock generation (OPCG) has been used for many years, often in conjunction with Logic and Memory BIST, but it is a labor-intensive process to identify the cutpoints and the OPCG behavior so the ATPG tools can ignore the OPCG logic. Supporting programmable OPCG logic in an ASIC methodology flow required us to automate the OPCG test generation flow. This paper describes how we provide a means for dealing with the programmable aspects of OPCG for use during ATPG and show some results for a few real designs.