Delay line control circuit e.g. for high speed reprogrammable delay line for integrated circuit tester, has fine and coarse delay lines to delay input clock signal sequentially

摘要

A fine delay line (12) outputs a fine delay signal based on the input clock signal. A coarse delay line (19) receives the fine delay signal and outputs a respective coarse delay signal. A latch unit outputs programmable control signal in response to the fine delay signal. A gating logic unit receives the coarse delay signal and outputs a gated delay signal. Independent claims are included for the following: (1) Polarity blanking delay circuit; and (2) Adjustable transients blanking circuit.