Since the invention of the transistor nearly six decades ago, new technology nodes have been added approximately every two years. This march of progress has yielded smaller transistors that run about 40% faster with each geometry scaling, fulfilling the promise and industry-defining mantra of "smaller, faster, cheaper!", and harder to Test. Now, in the realm of 65- and 45-nanometer design and manufacturing, the industry is confronted by multiple complex and stubborn challenges: silicon technology keeps shrinking, but doesn''''t advance in speed at the same rate. The recent high-k dielectric announcements have yet to be proven manufacturable, and copper interconnect is already hitting the wall. We are driving to the edge of the silicon roadmap, but there is no viable alternative to CMOS within our reach. Not coincidentally, several companies are announcing their intention to stop internal Ron6;D at the 45 nanometer node and use foundry-supplied processes at 32 nanometers and below. The electronics industry ecosystem is at a fork in the road: those few who can afford it will keep rushing to 45 nanometers and maybe beyond, to 32 and 25 nanometers; the rest will hold at 130 or perhaps 90 nanometers, trying to get the most out of those processes that they can. In both cases it is EDA that will come to the rescue. This is true for the Test area as well. We will show how new tools in test will be needed to keep up with these very hard requirements and how EDA Teat can help. EDA innovation is the gear that enables design for manufacturing and yield (which encompasses design for test), design for low power, and design for variability. EDA is not only the enabler for quality in electronic design; it is truly "where electronics begins!"
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