首页> 外文会议> >ALD metal-gate/high-/spl kappa/ gate stack for Si and Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFETs
【24h】

ALD metal-gate/high-/spl kappa/ gate stack for Si and Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFETs

机译:ALD金属栅极/高-/ spl kappa /用于Si和Si / sub 0.7 / Ge / sub 0.3 /表面沟道pMOSFET的栅极叠层

获取原文

摘要

ALD high-/spl kappa/ dielectrics and TiN metal-gate were successfully incorporated in both Si and Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFETs. The high-/spl kappa/ gate dielectrics used included Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/, Al/sub 2/O/sub 3//HfO/sub 2//Al/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/. The Si transistors with Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ showed a sub-threshold slope of 75 mV/dec. and a density of interface states of 3/spl times/10/sup 11/ cm/sup -2/ eV/sup -1/. No obvious degradation of the Si channel hole mobility was observed. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs with the various high-/spl kappa/ gate dielectrics demonstrated enhanced transconductance, drive current and channel hole mobility compared with the Si reference.
机译:ALD高-/ spl kappa /电介质和TiN金属栅已成功集成到Si和Si / sub 0.7 / Ge / sub 0.3 /表面沟道pMOSFET中。使用的高/ spl kappa /栅极电介质包括Al / sub 2 / O / sub 3 // HfAlO / sub x // Al / sub 2 / O / sub 3 /,Al / sub 2 / O / sub 3 // HfO / sub 2 // Al / sub 2 / O / sub 3 /和Al / sub 2 / O / sub 3 /。具有Al / sub 2 / O / sub 3 // HfAlO / sub x // Al / sub 2 / O / sub 3 /的Si晶体管的亚阈值斜率为75 mV / dec。界面状态的密度为3 / spl乘以10 / sup 11 / cm / sup -2 / eV / sup -1 /。没有观察到Si沟道空穴迁移率的明显降低。与Si基准相比,具有各种高/ spl kappa /栅极电介质的Si / sub 0.7 / Ge / sub 0.3 / pMOSFET表现出增强的跨导,驱动电流和沟道空穴迁移率。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号