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Method for making very low V_tmetal-gate/high-κ CMOSFETs using self-aligned low temperature shallow junctions

机译：利用自对准低温浅结制作非常低的 V _{t 金属栅/高κCMOSFET的方法}

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This invention proposes a method for making very low threshold voltage (V_t) metal-gate/high-κ CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low V_tof +0.05 and 0.03 V, high mobility of 90 and 243 cm²/Vs, and small 85° C. bias-temperature-instability 32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS. 展开▼

机译：本发明提出了一种使用新颖的自对准低温超浅结且具有与VLSI兼容的栅极优先工艺来制造极低阈值电压（V _{t ）金属栅/高κCMOSFET的方法。在1.2 nm等效氧化物厚度（EOT）时，良好的有效功函数为5.3和4.1 eV，V _{t 的+0.05和0.03 V低，迁移率分别为90和243 cm ^{2 / Vs和p-和n-MOS的85°C较小的偏置温度不稳定性<32 mV（10 MV / cm，1小时）。}}} 展开▼

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公开/公告号US7754551B2

专利类型

公开/公告日2010-07-13

原文格式PDF

申请/专利权人 ALBERT CHIN;
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申请/专利号US20080216561

发明设计人 ALBERT CHIN;
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申请日2008-07-08

分类号H01L21/00;H01L21/84;H01L21/338;H01L21/22;H01L21/38;

国家 US

入库时间 2022-08-21 18:52:23

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Method for making very low Vt metal-gate/high-κ CMOSFETs using self-aligned low temperature shallow junctions

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Method for making very low V_tmetal-gate/high-κ CMOSFETs using self-aligned low temperature shallow junctions