A statistical design methodology of a 0.12-/spl mu/m CMOS device for MPU applications

摘要

We designed a 0.12-/spl mu/m CMOS device using TCAD statistical simulation. We investigated techniques to reduce subthreshold leakage currents (Ioff) without degrading device performance to make IDDQ tests effective for large-scale and high-performance MPUs. Roll-off characteristics of threshold voltages were optimized considering process variations and maximum Ioff limitations. We demonstrated that a device with relatively large roll-off characteristics is superior to a conventional one in terms of MPU operation frequency.