A floating-body charge monitor circuit for partially depleted SOI CMOS

摘要

This paper presents a floating-body charge monitor technique, which does not require the use of body contacts. This technique improves the performance and timing robustness of MUX-type and SRAM bit line circuits on partially depleted (PD) SOI CMOS. It can also be used as a calibration tool for SOI device models by virtue of its direct body charge monitoring.