For large high-speed globally synchronous ASICs, designing the clock distribution net becomes a troublesome task. Besides problems caused by clock skew, the clock net also is a major source of power consumption. Partitioning the design into locally clocked blocks reduces clock skew problems and if handled correctly it also helps reducing power consumption. However, to achieve these positive effects, the blocks need on-chip clocks having properties as small area and low power consumption. Therefore, a low power small area digitally controlled on-chip clock generator is designed.
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