CLOCK SCHEME FOR GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS (GALS) CIRCUITS ON FPGA

摘要

Clock scheme for FPGA implementation of globally asynchronous locally synchronous circuits to achieve low power dissipation by reducing switching power consumption in a circuit is invented. Clock scheme for globally asynchronous locally synchronous (GALS) using clock divider and decoder module. Clock divider and decoder module mainly divides a global clock into low switching rate control signals that simplifies in circuit clock management modules and reduce global clock rate. Global clock is finely partition to the low rate control signals that results in low power dissipation with less complex circuitry and most importantly facilitates FPGA implementation.