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An investigation of single crystal Co-SALICIDE (self-aligned silicide) process for deep sub-micrometer CMOS devices

机译:深亚微米CMOS器件的单晶Co-SALICIDE(自对准硅化物)工艺研究

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In this paper, the Co-SALICIDE process has been investigated intensively for the application to deep sub-micron CMOS VLSI. Adopting a Co/Ti/Si structure, epitaxial growth of a single crystal CoSi/sub 2/ film on the [100] Si substrate through two-step RTA has been demonstrated in detail. The heat-reaction characteristics of the Co/Ti/Si structure for forming the single crystal CoSi/sub 2/ film have been studied. We have applied the single crystal CoSi/sub 2/ to SALICIDE process post junction fabrication to obtain a smoother interface. Focusing on the disadvantage of a large leakage current that Co-salicided diodes usually suffer, ultra-shallow junctions especially, we found the leakage current to be large and investigated several methods to reduce diode leakage. The experiments show that PAI can improve the inverse I-V characteristics remarkably. A leakage current density of a Co-salicided diode as low as 8/spl times/10/sup -8/ A/cm/sup 2/ (V=5 v) was obtained for a junction depth of 107 nm. The resistivity of the single crystal CoSi/sub 2/ film is 16.5 /spl mu//spl Omega//sub (BH)/cm.
机译:本文针对Co-SALICIDE工艺在深亚微米CMOS VLSI中的应用进行了深入研究。采用Co / Ti / Si结构,已通过两步RTA详细证明了单晶CoSi / sub 2 /膜在[100] Si衬底上的外延生长。研究了用于形成单晶CoSi / sub 2 /膜的Co / Ti / Si结构的热反应特性。我们将单晶CoSi / sub 2 /应用于SALICIDE工艺的结后制造过程,以获得更平滑的界面。针对钴化硅二极管通常会遭受的大泄漏电流的缺点,特别是超浅结,我们发现泄漏电流很大,并研究了几种减少二极管泄漏的方法。实验表明,PAI可以显着改善I-V逆特性。对于107nm的结深度,获得了共硅化的二极管的漏电流密度低至8 / spl乘以/ 10 / sup -8 / A / cm / sup 2 /(V = 5v)。单晶CoSi / sub 2 /膜的电阻率为16.5 / splμ// splΩ// sub(BH)/ cm。

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