CMOS implementation of a pulse-coded neural network with a current controlled oscillator

摘要

This paper presents a compact architecture for CMOS implementation of a pulse-coded neural network with a current controlled oscillator. A computational style described in this paper mimics a biological neural system using pulse-stream signaling and analog summation and multiplication. Synaptic weights are multiplied by employing current mirrors and choosing proper W/L ratios of output transistors of the pulse-coded neuron cell.