Low Threshold Voltage CMOSFETs with NiSi Fully Silicided Gate and Modified Schottky Barrier Source/Drain Junction

摘要

Low threshold voltage CMOSFETs with NiSi fully silicided gate and Modified Schottky barrier source/drain junction were fabricated. Symmetric threshold voltage was obtained by implant-to-silicide technique. Lateral growth rate and thermal stability of NiSi on SiO2 were investigated. Single silicide and low temperature process make the proposed process very promising in sub-45nm technology nodes.