Fabrication of poly-Si TFT with silicided Schottky barrier source/drain, high-κ gate dielectric and metal gate

摘要

In this paper, a polycrystalline Si thin film transistor (TFT) with self-aligned silicide Schottky barrier source/drain (SSD), high-κ gate dielectric and metal gate electrode is demonstrated using a simplified low temperature process. After crystallization of α-Si, the thermal budget for device fabrication is reduced to ～420℃ due to elimination of the implant doping and subsequent activation annealing procedures. P-channel SSD-TFT with PtSi S/D shows an acceptable electrical performance with I_(on) of 1.5 μA/μm for the L_g = 2.5 μm device at V_(gs) = V_(ds) = -5 V and I_(on)/I_(off) ratio of ～10~4. However, I_(on) of the n-channel SSD-TFT with DySi_(2-x) S/D is about two orders of magnitude smaller due to the relatively high Schottky barrier height and poor silicide quality of the DySi_(2-x)/poly-Si contact.