Data compression for system-on-chip testing using ATE

摘要

The manufacturing test of Systems-on-Chip (SoC) requires new design considerations for automatic test equipment (ATE). Compression has beers used in ATE to reduce storage and application time for high volume data by exploiting the repetitive nature of test vectors. Furthermore, the availability of boundary scan and the stringent integration requirements in the design of a head in an ATE necessitate a hardware-based technique which does not impact performance due to an excessive time complexity. The application of a binary compression method to an ATE environment for manufacturing test is studied using a technique, referred to as Reuse. In Reuse, compression is achieved by partitioning the vector set and removing repeating segments. This process has O(n/sup 2/) time complexity for compression (where n is the number of vectors) with a simple hardware decoding circuitry. It is shown that for industrial SoC designs; the efficiency of the Reuse compression technique is comparable with sophisticated software compression techniques with the advantage of easy and fast decoding (decoding is performed using shift registers which can be incorporated into the boundary scan or the head).