A timing verifier and timing profiler for asynchronous circuits

摘要

A system for timing verification and timing profiling of asynchronous circuits is presented. A hierarchical netlist is simulated with an ordinary simulator such as HSPICE. Signal transition information is extracted from the simulation results. The system uses this information and the netlist to compare the circuit to generalized signal transition graph specifications by simulating the flow of tokens in the graphs. If a signal makes a transition that is not allowed by the specification, a timing error has occurred. The flow of tokens in the graph is also used to produce timing statistics for the circuit. Based on these statistics, timing optimization can be done in an iterative design process.