VLSI implementations of fast residue number system arithmetic units for one-hot encoded operands are presented. They are shown to allow generalized LFSRs (i.e., those with any modulus) to be implemented with faster clock speeds and simpler, more regular layouts. Their high speed is exemplified by the design of a non-uniform pseudo-random test pattern generator for performance testing of an ATM packet switch. Timing estimates of the generator indicate as much as a 50% increase in clock speed as compared with a standard design. The speed increase is made possible because the one-hot encoding eliminates the address decoding circuitry in the inverse probability distribution RAM.
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