One-hot residue coding for low delay-power product CMOS design

摘要

CMOS implementations of arithmetic circuits for One-Hot Residue (OHR) encoded operands are presented. They are shown to possess SPICE-simulated delay-power (DP) products that are significantly reduced below those of their binary number system counterparts (ripple-carry adder and Wallace tree multiplier). The reduction is attributable to the one-hot representation, which decreases the number of critical path transistors and signal activity factors. An OHR-based direct digital frequency synthesizer for frequency-hopped communication systems is presented, and analytical estimates of its DP-product are derived. The design exhibits a DP-product reduction in excess of 90% below that of a binary-encoded residue synthesizer.