MOSIZ: a two-step transistor sizing algorithm based on optimal timing assignment method for multi-stage complex gates

摘要

A description is given of a novel hierarchical timing assignment method, for the transistor sizing of multistage MOS circuits. The approach is composed of two steps: the first is the optimal timing assignments to logic stages in possible logical paths; and the second is the optimization of the sizes of all the transistors in each stage to realize the timing assignments. Compared with unsized circuits, the sizing results showed that this approach can improve both the delay and response characteristics of the circuits, and CPU time is essentially less than for conventional methods for the long stages.