Identification of Logic Paths Influenced by Severe Coupling Capacitances

摘要

Modern integrated circuits present complex interconnect structures, in which the signal coupling play an important role in the overall circuit behavior. In this paper, a method to identify those logic paths more significantly influenced by signals at coupled lines is presented. This method can be used to validate circuit behavior and can also be applied in testing techniques oriented to detect interconnect defects (e.g. opens and short defects). A modified Dijkstra's algorithm is used to find those paths between a primary input and a primary output with higher coupling capacitances. This methodology is applied to ISCAS'85 benchmark circuits.