Reduction of the Wafer Backside Chips and Crack in the Backend of the Line Wafer Manufacturing Process

摘要

This paper describes process improvements that have been implemented to reduce wafer backside edge chips and cracks. The induced cracks generated at the end of the process line can be detrimental. During Parametric Testing (PT) or Electrical Wafer Sort (EWS) the chipped wafer may shatter into pieces, hence impacting the company's revenues. Figure 1 below shows chips and cracks induced from backend processes.