A High-Speed Area-Efficient Architecture for the Arithmetic in GF(2~m)

摘要

Finite fields have been used for numerous applications including error-control coding and cryptography. This paper presents a high-speed area-efficient architecture for arithmetic that can support arbitrary irreducible polynomials in GF(2~m). The arithmetic unit can perform the Galois field arithmetic operations of addition, subtraction, multiplication, squaring, inversion and division. The least significant bit first (LSB-first) scheme for modular multiplication and the extended Euclid's algorithm for modular inversion are both modified for the arithmetic unit. The architecture has been implemented using 0.18-μm CMOS standard cell library, the clock frequency can reach 300MHz for a 512-bit arithmetic unit. The gate count of the circuit is only 48528.