DESIGN OF A MULTIPLIER WITH LOW POWER DATA COMPRESSORS

摘要

A parallel structured 54 × 54 bit multiplier with low power data compressors is proposed. Using a tally-function circuit [1], an optimized low power data compressor is designed The average power consumption of the proposed data compressor is reduced by about 35%, compared with that of the conventional multiplier [2] ; while the propagation delay is nearly same as that of the conventional one.