Parallel Processing for Ray/Bezier Patch Intersection Computation - A Software/Hardware Co-Design Approach

摘要

We describe an algorithm for computing ray/Bezier patch intersections. This algorithm uses patch subdivision and other geometrical techniques to find a given maximum number of intersection points nearest to the ray origin. Based on the algorithm, we propose a parallel, pipelined hardware architecture, verify the number of pipeline stages required through simulation, and estimate the performance of a load-balanced implementation based on state-of-the-art digital signal processors (DSPs) and custom designed ASIC, via a software/hardware co-design approach.