Sequential Logic Optimization with Implicit Retiming and Resynthesis

摘要

This paper's introduces a new logic transformation that integrates retiming with algebraic and Boolean transformations at the technology-independent level. It offers an additional degree of freedom in sequential network optimization resulting from implicit retiming across logic blocks and fanout stems. The application of this transformation to sequential network synthesis results in the optimization of logic across register boundaries. We have implemented our new technique within the SIS framework and demonstrated its effectiveness in termso f cycle-time minimization on a set of seuqential benchmark circuits.