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Pipelined 8-bit RISC processor design using Verilog HDL on FPGA

机译:在FPGA上使用Verilog HDL的流水线8位RISC处理器设计

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This article describes an 8-bit RISC processor design using Verilog Hardware Description Language (HDL) on FPGA board. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. The salient feature of proposed processor is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. Another important feature is that instruction set contains only 34 instructions, which is very simple, easy to learn and compact. The proposed processor has 8-bit ALU, Two 8-bit I/O ports, serial-in/serial-out ports, Eight 8-bit general-purpose registers, 4-bit flag register and priority based three vectored interrupts. Another advantage of the proposed processor is that it can execute programs with up to 262,144 instructions long, such that any practical programs can be fitted into it. The proposed processor is physically verified on Xilinx Spartan 3E Starter Board FPGA with 0.0517μs instruction cycle.
机译:本文介绍了在FPGA板上使用Verilog硬件描述语言(HDL)的8位RISC处理器设计。所提出的处理器是使用哈佛架构设计的,具有独立的指令和数据存储器。所提出的处理器的显着特征是流水线,用于提高性能,以便在每个时钟周期执行一条指令。另一个重要功能是,指令集仅包含34条指令,非常简单,易学且紧凑。拟议的处理器具有8位ALU,两个8位I / O端口,串行输入/串行输出端口,八个8位通用寄存器,4位标志寄存器和基于优先级的三个向量中断。所提出的处理器的另一个优点是它可以执行长达262,144条指令的程序,从而可以在其中安装任何实用程序。所提出的处理器已在Xilinx Spartan 3E入门板FPGA上以0.0517μs的指令周期进行了物理验证。

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