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Design of lightning acquisition and smart triggering using Kintex-7 FPGA and NI cRIO

机译:使用Kintex-7 FPGA和NI cRIO设计雷电采集和智能触发

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In this paper, we present the approach as well as obtained results for high speed data acquisition and real time processing of lightning data on the Lightning Sensor Node. The current paper focuses on the digital implementation details on the Lightning Sensor Node. The data acquisition and processing is carried out on the Kintex-7 FPGA. The setup comprises of a cRIO-9030 chassis along with the I/O modules mounted on it and a Kintex-7 FPGA. The various data acquisition steps and the processing algorithm have been implemented on the Kintex-7 FPGA. The cRio-9030 controller is only used for handling the communication from the Controller to the PC using Ethernet. The data acquisition basically comprises of sampling using ADC at the rate of 1 MS/s using NI 9223 ADC module and GPS time stamping for relevant sample value acquired using the ADC module. The NI 9467 module is used for the GPS time stamping purpose. The sampling at such a high rate results in a lot of unwanted data being buffered and tends to increase the processing overhead. Hence, we have further implemented a smart triggering on the FPGA. The FPGA now sends a limited chunk of data in the form of a frame consisting of 35 data points along with the relevant timestamps in microseconds. The data obtained after applying the Smart Triggering algorithm is now dispatched to the cRIO controller using the FPGA to Real Time DMA FIFO. The DMA FIFO used here initiates a high speed data transfer. The cRIO is now utilized to reconstruct the timestamps and data values obtained from the FPGA and later implement the communication to the PC using Ethernet.
机译:在本文中,我们介绍了闪电传感器节点上闪电数据的高速数据采集和实时处理的方法以及获得的结果。本白皮书重点介绍闪电传感器节点上的数字实现细节。数据采集​​和处理在Kintex-7 FPGA上进行。该设置包括一个cRIO-9030机箱以及安装在其上的I / O模块和Kintex-7 FPGA。各种数据采集步骤和处理算法已在Kintex-7 FPGA上实现。 cRio-9030控制器仅用于处理使用以太网从控制器到PC的通信。数据采集​​主要包括使用NI 9223 ADC模块以1 MS / s的速率使用ADC进行采样以及使用ADC模块采集的相关采样值的GPS时间戳。 NI 9467模块用于GPS时间戳记。如此高的采样率导致大量不想要的数据被缓存,并倾向于增加处理开销。因此,我们进一步在FPGA上实现了智能触发。 FPGA现在以帧的形式发送有限的数据块,该帧由35个数据点以及相关的时间戳(以微秒为单位)组成。现在,使用智能触发算法后获得的数据通过FPGA到实时DMA FIFO分配给cRIO控制器。此处使用的DMA FIFO启动高速数据传输。现在,利用cRIO重构从FPGA获得的时间戳和数据值,然后使用以太网实现与PC的通信。

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